alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
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Verilog AXI components for FPGA implementation
The USRP™ Hardware Driver Repository
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Plugins for Yosys developed as part of the F4PGA project.
HDL libraries and projects
SystemC/TLM-2.0 Co-simulation framework
Verilog library for ASIC and FPGA designers
PicoRV32 - A Size-Optimized RISC-V CPU
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
C implementation of the Mersenne Twister pseudo random number generator algorithm. While it is initially intended for the PolyLogic project, I may end up using it in other instances where I need a good RNG.
SERV - The SErial RISC-V CPU
